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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
18-Bit Switchable Active SCSI Bus Terminator (110)
The MCCS142235TM is a precision 18-bit switchable active SCSI bus terminator. It is used in conjunction with a 2.85V regulator (MC34268). Also provided is a Local-VCC (LVCC) low voltage sense circuit to latch the enable state when a peripheral is shut down or loses power. When the device is enabled according to the truth table below, the MCCS142235 provides 110 precision resistor pull-ups to a 2.85V reference for termination of 18-bits in a SCSI standard bus system interface. When the switch is disabled, the device is in a High Impedance State on all 18 bits. The low voltage sense circuit gives the device the ability to latch the current output state when power is removed from the LVCC pin. As long as TERMPWR remains, there is no interruption to the SCSI bus when powering down a SCSI peripheral, because the proper termination condition remains. In 8-bit SCSI applications ("A" cable), only one `2235 is needed at each end of the SCSI cable in order to terminate the 18 active signal lines. In 16-bit WIDE SCSI applications ("P" cable), one `2235 and one `2234 (or two `2235s) would be needed at each end of the SCSI cable in order to terminate the 27 active signal lines. For information on "Power Dissipation for Active SCSI Terminators," refer to Motorola Application Note AN1408/D, available through the Motorola Design-NET Fax System, or through the Motorola Literature Distribution Center.
MCCS142235
18-BIT ACTIVE SCSI TERMINATOR (110)
DW SUFFIX 24-LEAD WIDE SOIC PACKAGE CASE 751E-04
* * * * *
Complies With SCSI and SCSI-2 Standards 18 Switchable 110 Terminating Resistors Operating Temperature Range: 0C to 70C Operating Voltage Range: 2.75 to 2.95V
FA SUFFIX 32-LEAD PLASTIC FQFP PACKAGE CASE 873A-02
Resistor Tolerance 5.0% (Over Temperature and Supply Voltage Ranges) * Local-VCC (LVCC) Low Voltage Sense Circuit TRUTH TABLE Test Active Mode Test Mode
VREG LVCC O18 24 23 22 O17 21
Enable 0 1 X
Output Z Terminated Test Mode
0 0 1
O16 20
O15 19
O14 18
O13 17
O12 16
O11 15
O10 14
Test 13
MCCS142235
1
2
3 O1
4 O2
5 O3
6 O4
7 O5
8 O6
9 O7
10 O8
11 O9
12 GND
Vref Enable
Figure 1. 24-Lead Pinout (Top View)
MCCS and Mfax are trademarks of Motorola, Inc. 1/97
(c) Motorola, Inc. 1997
1
REV 2
MCCS142235
Heat Sink*
32 31 30 29 28 27 26 25 Heat Sink* O2 O3 O4 O5 O6 O7 Heat Sink* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 *NOTE: All Heat Sink pins are electrically isolated from the circuit. Tie to largest heat sink. 24 23 22 21 Heat Sink* O17 O16 O15 O14 O13 O12 Heat Sink*
MCCS142235
Heat Sink* 20 19 18 17 Heat Sink* VREG 110 Output 1
Enable
VREG
LV CC O10
GND
O8
O9
Test
Heat Sink*
Figure 2. 32-Lead Pinout (Top View)
LVCC 60k 60k + - 110 Output 2
Vref Enable 100k Test 20k Enable Logic & Latch Circuitry 110 Output 18
O11
O18
Vref
O1
Ring Oscillator & Charge Pump
CIRCUIT DESIGN PATENT PENDING
Figure 3. MCCS142235 Block Diagram
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SCSI TERMINATORS BR1486
MCCS142235
5.0V 0.5V 1N5819 DEVICE #1 TERMPWR DEVICE #2
MC34268* VIN 10F 5.0V 0.5V VOUT 10F
2.85V
MC34268* VIN 10F 5.0V 0.5V VOUT 10F
2.85V
MCCS142235 LVCC VREG SYSTEM LOGIC Enable O1 Vref O18 SYSTEM LOGIC
MCCS142235 LVCC Enable O1 VREG Vref O18
SCSI BUS 1
SCSI RECEIVERS
SCSI RECEIVERS
SCSI BUS 18
OPEN COLLECTOR SCSI BUS DRIVER
OPEN COLLECTOR SCSI BUS DRIVER
*For More Application Information Refer to the MC34268 Datasheet.
Figure 4. Typical SCSI Bus Configuration Using the MCCS142235
MAXIMUM RATINGS* Symbol
VREG Vin Vin Vout Iin Iout ICC Tstg TL
Parameter
DC Regulated Power Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) for Test/Vref pins DC Input Voltage (Referenced to GND) for LVCC/Enable pins DC Output Voltage (Referenced to GND) DC Input Current, per pin DC Output Current, per pin DC Supply Current, VREG and GND pins Storage Temperature Lead Temperature, 1mm from case for 10 seconds
Value
-0.5 to 3.0 - 0.5 to VREG + 0.5 - 0.5 to + 6.0 - 0.5 to VREG +0.5 20 35 500 - 65 to + 150 260
Units
V V V V mA mA mA C C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
SCSI TERMINATORS BR1486
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MCCS142235
RECOMMENDED OPERATING CONDITIONS Symbol
VREG Vin, Vout Vin TA tr, tf tr, tf
Parameter
DC Regulated Power Voltage (Referenced to GND) DC Input Voltage (Test/Vref Inputs) DC Input Voltage (Enable, LVCC Inputs) Operating Temperature Input Rise and Fall Time (All inputs but LVCC) Input Rise and Fall Time (LVCC)
Min
2.75 0 0 0 0 0
Max
2.95 VREG 5.5 70 500 no limit
Units
V V V C ns ns
DC CHARACTERISTICS
VREG Symbol VIH VIL Iin Parameters Min High-Level Input Voltage Max Low-Level Input Voltage Max Input Leakage Current (Enable Input) Max Input Leakage Current (Test Input) Max Input Leakage Current (LVCC Input) (V) 2.85 2.85 2.85 2.85 2.85 2.85 Max Input Leakage Current (Vref Input) IOZ Max Output Leakage Current Max Quiescent Supply Current ICC Max Quiescent Supply Current (Comparator Active) Max Quiescent Supply Current (Comparator Active/ Termination Active) 2.85 2.85 100 800 200 1000 A A 2.85 2.85 2.85 Min 2.0 0.8 0.10 0.10 0.10 100 0.10 0.50 1.0 25C Max 0C to + 70C Min 2.0 0.8 1.0 1.0 1.0 200 1.0 5.0 10 Max Unit V V A A A A A A A Condition Per Truth Table Per Truth Table Vin = GND Vin = GND Vin = GND Vref = GND Vin = 5.5V Vref = GND Vin = VREG LVCC = VREG Per Truth Table Vout = GND or VREG Vref/LVCC = VREG Enable/Test = GND Enable/Vref/Test = GND LVCC = 5.0V Test/Vref = GND Enable/LVCC = 5.0V Iout = 0A
TERMINATION RESISTOR CHARACTERISTICS
VREG (V) Symbol R110 Parameters Output Termination Impedance (Note 1.) Min 2.75 Max 2.95 Min 108.9 (Note 1.) 35C Max 111.1 (Note 1.) 0C to + 70C Min 104.5 Max 115.5 Unit Condition Per Truth Table
1. See Figure 5, Termination resistance versus regulated supply voltage and temperature. 110 Resistor Target Is at 35C. Temperature coefficient of resistance TC = 0.135/C typical.
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SCSI TERMINATORS BR1486
MCCS142235
70 63 56 49 112 TEMPERATURE (C) 42 35 28 21 14 7 0 2.75 109 108 107 106 105 104 R110 () 2.77 2.79 2.81 2.83 2.85 VREG (V) 2.87 2.89 2.91 2.93 2.95 Parameter Latch Voltage (LVCC Input) Output Capacitance High Impedance VREG (V) 2.85 2.85 Typical @ +25C 3.70 8.0 Unit V pF Per Truth Table Per Truth Table, Output = 0V 45 VREG Terminated 65 Output High Impedance 10pF 111 110 115 114 113
Figure 5. Termination Resistance R110 () versus Regulated Supply Voltage VREG (V) and Temperature (C) (Model Adj R-Sq = 0.9995)
DC CHARACTERISTICS
Symbol VT Cout Condition
Figure 6. Output Impedance Model
SCSI TERMINATORS BR1486
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MCCS142235
AC CHARACTERISTICS (VREG = 2.85, CL = 50 pF, tr = tf = 6 ns)
Symbol t(Enable) Parameters Max Propagation Delay, High Impedance to Termination, Enable to Outputs Max Propagation Delay, Termination to High Impedance, Enable to Outputs 0C to + 70C 100 Unit s Per Truth Table Condition
t(Disable)
1.0
s
Per Truth Table
TIMING REQUIREMENTS (VREG = 2.85, CL = 50 pF, tr = tf = 6 ns)
Symbol tsetup thold Parameters Min Setup Time, LVCC to Enable Min Hold Time, LVCC to Enable 25C 200 50 0C to + 70C 500 100 Unit ns ns (See Figure 7) (See Figure 7) Condition
VCC V LVCC 3.7V 3.7V 0.0 V tsetup Enable thold enabled 50% disabled 50% VCC V 0.0 V
* If LVCC Enable is grounded then the LVCC feature is disabled. Figure 7. Timing Requirements
MCCS142235 Applications Information
Proper Use of the LVCC Feature The Motorola Active SCSI Terminator chip incorporates features not available in competitor designs. A primary feature, known as "Local VCC sensing", facilitates future migration to reliable software control of the termination state (either terminated or high impedance). When the Enable pin is driven by internal logic within the SCSI peripheral, it is essential that the peripheral be powered up. Otherwise the enable signal to the termination chip may be invalid causing system bus failure due to improper termination. Imagine a SCSI system with a disk drive at one end of the bus which is providing termination to the bus via the MCCS142235 device. A "smart" drive will be providing an enable signal to the termination chip through internal logic circuitry to ensure termination is present. In the event this same disk drive is powered down by a user while the bus is active, what becomes of the termination located within that drive? Does it remain terminated? Does it change state causing the system to crash? Or does it go into an undetermined state? The termination power supply is always present on an operating SCSI bus through the dedicated TERMPWR line. But the "Local VCC" power supply within each peripheral may be powered down at any time while the SCSI bus is in operation. It is this local supply which powers the peripheral's logic chips and provides the enable signal to the SCSI terminator chip. Therefore, it is essential to maintain the proper enable signal to the switchable terminator even during peripheral power down.
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EEEEEE EEEEEE EEEEEE
SCSI TERMINATORS BR1486
MCCS142235
To avoid rendering the system inoperable while powering down a terminating peripheral, Motorola has an exclusive "Local VCC sensing" circuit on the MCCS142235 which latches the enable state of the termination permanently during peripheral power loss. A comparator within the MCCS142235 can be connected to the local power supply via the LVCC input. The LVCC level is monitored against an internal reference, and the current enable state is latched should LVCC drop below a predetermined value (3.70V). This comparator threshold is set sufficiently high to ensure that a valid logic state still exists on the TTL-level Enable pin prior to latching. Upon return of the local power supply, the enable path automatically becomes transparent, and the termination state returns to system control! The Local VCC sensing feature has been designed to draw as little DC current as possible. Flexibility has been designed into the MCCS142235 to allow the Local VCC sensing feature to be disabled when not required. In this disabled state, the DC bias current is completely removed and the enable latch remains transparent at all times. Figure 8 shows the recommended connection scheme to utilize the LVCC latch feature. Figure 9 shows the recommended connection scheme for applications in which the LVCC feature is not required - the LVCC and Vref pins are shorted to VREG and the enable path remains permanently transparent.
1 Enable Signal Driven by Logic Chip Output. 2 3 4 5 6 7 8 9
Vref Enable O1 O2 O3 O4 O5 O6 O7
VREG 24 LVCC 23 O18 22 O17 21 O16 20 O15 19 O14 18 O13 17 O12 16 O11 15 O10 14 Test 13
Connect to 2.85V Regulated Supply. Connect to VCC Supplying Board-Level Logic. DO NOT Connect to TERMPWR. When LVCC 3.7V, the Termination State Will Be Determined by the Enable Signal (Per Truth Table). When LVCC 3.7V, the Enable Signal Will Be Latched. Termination Will Remain in the Proper State as Long as VREG (ie TERMPWR) Is Present.
10 O8 11 O9 12 GND
Figure 8. Recommended Connection Scheme to Utilize LVCC Feature
SCSI TERMINATORS BR1486
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MOTOROLA
MCCS142235
1 Enable Signal Driven by Hardware Switch or Jumper. 2 3 4 5 6 7 8 9
Vref Enable O1 O2 O3 O4 O5 O6 O7
VREG 24 LVCC 23 O18 22 O17 21 O16 20 O15 19 O14 18 O13 17 O12 16 O11 15 O10 14 Test 13
Connect to 2.85V Regulated Supply.
Enable Latch Will Be Transparent as Long as VREG (ie TERMPWR) Is Present. DC Standby Current for All Analog Circuitry Associated With LVCC Will Be Eliminated.
10 O8 11 O9 12 GND
Figure 9. Recommended Connection Scheme to Disable LVCC Feature
Enable Input Application A. No Connection to Enable
Result
Enable input will be pulled "LOW" internally. Termination will be disabled causing all outputs to be high impedance. Enable input will be pulled "LOW" internally when the switch is open. Enable input will be held "HIGH" when the switch is closed. The supply source in this case could be TERMPWR, VREG or VCC. This is a more expensive way to accomplish application B. above. It is more eco- nomical to allow the internal pulldown to provide the "LOW" input level. The Supply Source in this case could be TERMPWR, VREG or VCC. The MCCS142235 will be permanently disabled causing all outputs to be high impedance. The MCCS142235 will be permanently enabled providing 110 nominal impedance to each bus line. With LVCC input connected to the local power supply and Vref connected to GND, the Local-VCC sensing and Enable latching feature will be active. If this feature is not desired, tie LVCC and Vref to VREG (per Figure 9), and the Enable state will follow the Truth Table.
B. Single Pole Switch to Supply
C. Double Pole Switch Between Supply and GND
D. Hardwired "Low"
E. Hardwired "High"
F. External Logic Driven
MOTOROLA
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SCSI TERMINATORS BR1486
MCCS142235
OUTLINE DIMENSIONS
FA SUFFIX FQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
SCSI TERMINATORS BR1486
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
9
-T-, -U-, -Z- MOTOROLA
EE EE EE
MCCS142235
OUTLINE DIMENSIONS
DW SUFFIX SOIC PACKAGE CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
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MOTOROLA 10
MCCS142235/D SCSI TERMINATORS BR1486

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